1. Field of Invention
This invention relates to improvements in digital-to-analog converters and methods for constructing and operating same, and more particularity to digital-to-analog converters having improved linearity and methods for constructing and operating same.
2. Background Information
Digital-to-analog converters (DACs) are circuits used to convert digital codewords into analog signals. Each codeword that is applied to the digital input of the DAC represents a quantized value that is converted by the DAC into a corresponding analog value at its output according to the transfer function of the DAC. Typically, but not necessarily, each bit of the digital input codeword is weighted as a function of the position of the respective bits within the codeword. When the position weights of each of the bits in a codeword are summed, they produce a value to be represented by the magnitude, typically the voltage magnitude, of the analog output signal.
However, offset, gain, and integral linearity (INL) of ordinary DAC circuits are imperfect, and often result in the analog output values having an error component from that desired. (INL error is the maximum deviation of an actual transfer function of a DAC from the ideal transfer function of the DAC, after the effects of offset and gain errors are mathematically removed from the actual transfer function of the DAC.)
What is needed, therefore, is a circuit and method for improving or reducing the error or deviation of the main DAC circuit in converting a digital data input to analog output values, so that the output is produced more closely following a desired transfer function. The circuit and method are needed to replace expensive laser-trimming techniques that are widely used in the industry.
In light of the above, therefore, it is an object of the invention to provide an improved digital-to-analog converter that has improved linearity and methods for constructing and operating same.
It is another object of the invention to provide an improved digital-to-analog converter of the type described that can be calibrated in a one-pass test flow.
The present invention presents a digital-to-analog converter (DAC) with digital calibration to improve the overall integral nonlinearity (INL) performance. In one embodiment, the architecture includes of a 10 bit resistor string that decodes the 10 most significant bits (MSBs) and a 6 bit interpolating amplifier, which is used to decode the 6 least significant bits (LSBs). The DAC has digital calibration to improve INL characteristics. The resistor string architecture alone has good differential nonlinearity (DNL) characteristics, but suffers from high INL errors. Thus, transfer function errors of the DAC are computed during final test at specific points. The errors at these points are coded into permanent on-chip memory as control points. These control points then drive digital circuits that implement the math for piece-wise linear calibration waveform generation. A calibration DAC then sums the inverse of the error voltage to correct for the offset gain and linearity errors.
One calibration approach of the invention is to digitally calibrate the DAC based on the performance results obtained from a tester. At the time of final testing, the INL is evaluated using the standard linearity test methods. The INL values at certain specific codes are stored in registers. This can be achieved, for example, by blowing certain fuses based on the values read from the tester. The calibration module then uses the values stored by fuse blowing, and the DAC calibrates itself by subtracting an approximation to its INL curve. The approach of the invention does not actually modify the architecture of the DAC, but digitally calibrates its performance. This is achieved by calculating the INL from the tester and then adding or subtracting a desired amount of signal to or from the output of the main DAC before the signal is outputted from the device. In a preferred embodiment, this requires an additional calibration DAC along with the main DAC.
According to a broad aspect of the invention, a method is presented for constructing a calibrated digital-to-analog converter (DAC). The method includes developing predetermined functions between adjacent pairs of selected digital input code values approximating deviations of actual analog output values of a main DAC from desired analog output values of the main DAC and configuring a programmable circuit to provide piecewise linear digital correction input values to a calibration DAC according to the piecewise linear functions. The calibration DAC provides analog correction values for subtraction from an analog output of the main DAC to provide calibrated analog output values. Preferably, the predetermined functions are piecewise linear functions.
According to another broad aspect of the invention, a method is presented for constructing a calibrated digital-to-analog converter (DAC). The method includes providing an uncalibrated main DAC having a digital input and an analog output. When digital input signal values are applied to the digital input, corresponding analog output values are produced on the analog output. A deviation of an actual analog output value from a desired analog output value is measured for each of a number of digital input code values, and sets of linearly varying values are developed between adjacent pairs of selected digital input code values. The sets approximate the measured nonlinearity values. A programmable circuit is configured to provide digital correction input values to a calibration DAC according to the linearly varying values. When a digital input code value is applied to the digital input of the main DAC, an analog output of the calibration DAC is subtracted from the analog output of the main DAC to provide a calibrated output value.
According to yet another broad aspect of the invention, a method is presented for constructing a digital-to-analog converter (DAC). The method includes constructing an uncalibrated DAC that includes a circuit for producing an analog output signal having a magnitude that corresponds to a digital input according to a predetermined digital input signal code. A predetermined sequence of digital input signal codes produces corresponding analog output values according to an actual transfer function, a memory, and digital circuits configured to modify the digital input signal codes according to states contained in the memory. For each of predetermined digital input code values, a corresponding error value is determined representing a deviation of an actual value of the analog output produced by the actual transfer function from a desired analog output value according to a desired transfer function. States representing the corresponding error values are coded into the memory, and the digital circuits are operated to modify the predetermined digital input codes according to the states in the memory to produce the desired analog output values.
According to yet another broad aspect of the invention, a calibrated digital-to-analog converter (DAC) is presented. The DAC includes a main DAC having a digital input and an analog output. When digital input signal values are applied to the digital input, corresponding analog output values are produced on the analog output. A memory contains sets of linearly varying values between adjacent pairs of selected digital input code values. The sets approximate deviations of actual analog output values from desired analog output values. A calibration DAC has an analog output connected to be subtracted from the analog output of the main DAC, and a control circuit selects values from the sets of linearly varying values corresponding to input digital values to the main DAC and apply the selected values to the calibration DAC.
According to still yet another broad aspect of the invention, a calibrated digital-to-analog converter (DAC) is presented. The calibrated DAC includes a main DAC having a digital input and an analog output. When digital input signal values are applied to the digital input, corresponding actual analog output values are produced on the analog output. During final testing, integral linearity error (INL) is measured by the tester, and a subset of INL values called xe2x80x9ccontrol pointsxe2x80x9d are written to on-chip memory. Each control point datum in the memory has a first component that represents the digital input code at which a specific INL error occurs, and a second component that represents the value of the actual INL error at that specific digital input code. Each control point is spaced from an adjacent control point to contain a predetermined range of actual analog output values. Circuitry for generating linearly varying deviation values between two adjacent control points is provided to drive calibration DAC, which has an analog output connected to be subtracted from the actual analog output value of the main DAC. A control circuit selects a pair of control points, and the deviation values of the calibration DAC is obtained by interpolating the second components of adjacent control points when the digital input of the main DAC falls between the first components of these two adjacent control points.